Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build t

Lead a high performance engineering team Form a team and nurture talent Lead team, meet schedule commitments and provide strong support to customers Collaborate with multi functional leaders to drive AMD's success PREFERRED EXPERIENCE A strong leader with experience working with a distributed team Strong mentoring and coaching skills Proven experience managing and leading

Develop an industry leading software design entry solution for future AMD SoC devices. Ensure a seamless customer experience configuring and using our SoC devices. Ensure all hardware functionality is accounted for in our software solution. Actively contribute to writing software specifications with our engineering teams to ensure the robustness of the solution. Engage wi

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD

Analyzecomplex digital design problems and propose solutions Develop Verilog RTL and Functional Behavioral Models Drive/develop ASIC design flows and scripts Create microarchitecture specifications Work with Design Verification team to ensure functional correctness Work with Physical Design team to ensure proper implementation of the design along with timing closure Deliv

Root cause and address compiler crashes, miscompilation and performance bottlenecks. Build diagnostics tools for improving the triage process Enhance the testing infrastructure to ensure that this issues are caught early Engage with the community to coordinate similar efforts to ensure that the community can benefit from advances made here Ensure that the project is adher

Conduct full review of existing HPC EDA infrastructure with grid, OS, and EDA tools teams as well as engineering technical leaders and re architect the future global hybrid on prem and multi cloud HPC infrastructure that is highly efficient, utilized, scalable, and cost effective. Propose innovative approaches and work collaboratively with peer teams to maximize grid perf

Define and specify micro architecture of AI Engine building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirements RTL design and debug of complex blocks in Verilog / System Verilog Analyze design metrics and make implementation choices to optimize PPA Work with verification and physical design teams to achieve high quality des

Collaborate with AMD and VMware architects, Field Engineers, Partners and Customers to identify areas of integrations/enhancements/performance between AMD EPYC and VMware products. Work with stakeholders across companies to implement identified improvements end to end. Drive creation and publication of validated AMD EPYC based solutions on VMware product stack to drive cu

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL an

Analyze power consumption of new and existing micro architectural features of Next Generation High Performance CPU Cores. Analyze power characteristics of the latest Server/Client CPU workloads and use the data to influence microarchitecture decisions. Collaborate with the RTL team to improve the implementation. Asist them in interpreting power analysis results from tools

Define and implement Micro Architecture of Next Generation High Performance Processor Cores Collaborate with the Physical Design Team to achieve high frequency and low power while utilizing the latest cutting edge fabrication technologies Work with a team of Hardware and Software Engineers to advance the Instruction Set Architecture Collaborate with the Design Verificatio

Isolate generic system level failures into a more focused area of the platform or CPU Drive debug and resolution of Zen CPU validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed Devise validation strategy from pre silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams

Work with AMD's architecture specialists to improve future products. The ideal candidate will be responsible for writing high performance GPU kernels for AMD's Composable Kernel (https //github.com/ROCmSoftwarePlatform/composable_kernel) Performance Portable Programming Model for Machine Learning Tensor Operators. They will be developing and optimizing algorithms for new

Provide advisement and coordination for RPPG leadership team to drive decision making processes and execution of the strategic business objectives. Develop collaterals (presentations, pre reads, communications) for the CVP on internal and external activities through original contribution and/or collaboration with executives and senior leaders across RPPG. Represent the CV